The Future of Moore's Law: Dr. Gary Patton's Insights on Enabling Innovation

Dr. Gary Patton, the corporate vice president and general manager of Design Enablement Group in technology development for theel Corporation, is today's keynote speaker.

Dr. Patton discusses the transition from system on a chip to a system of chips to keep Moore's Law alive, highlighting five enablers for achieving this. One key enabler is for The Foundry business to shift from a silicon Foundry to a system Foundry.

The world generates 270,000 petabytes of data daily, with a projected average of one petabyte of compute and data per individual by 2030, emphasizing the need for continued innovation to support this growth.

Reflecting on the profound impact of the technology industry on society, Dr. Patton recalls milestones like the introduction of portable PCs and remote key fobs, highlighting the industry's evolution from luxury to ubiquity over the past 40 years.

The demand for chips supporting AI is rapidly increasing, with a 2X growth rate every 10 months, posing challenges in energy efficiency. AI is projected to consume nearly 100 terawatt-hours per year, equivalent to the energy usage of some countries.

Facing challenges in scaling and performance improvements, the industry aims to integrate packaging and silicon to evolve towards a concept called 'symore,' building on past innovations to overcome current obstacles.

Intel has showcased significant innovation in packaging, including standard packaging, two and a half and 3D packaging solutions like emib and verus forus direct. These innovations have led to a 10,000 increase in interconnect density and a 50x increase in Energy Efficiency, enabling advancements in system of chips.

The establishment of an industry standard for interconnect, particularly Universal chiplet interconnect Express (UCIE), allows for mixing and matching chips from different technologies and foundries. This standard provides high bandwidth, low latency, and flexibility in chip upgrades, enhancing the overall design process.

The UCIE standard has seen significant growth since its launch over two years ago, with 135 companies now part of this standard. This expansion is set to revolutionize systems of chips, offering substantial improvements in bandwidth density and Energy Efficiency, making it a game-changer in chip design.

System technology co-optimization involves optimizing silicon, packaging, and software architecture as a complete package to maximize power, performance, and area efficiency. This approach, akin to traditional design technology co-optimization, is poised to deliver more than a 2x performance improvement over the next two decades, ensuring continuous innovation in silicon and packaging technologies.

The shift from a silicon foundry to a systems foundry marks a key element of enablement, focusing on system solutions and technology co-optimization. This transition emphasizes combining innovations in silicon, packaging, memory, interconnects, system architecture, software, and firmware to deliver optimized system solutions, ensuring ongoing advancements in the field.

Intel's key Foundry offerings include Intel 16 and Intel 18a for manufacturing. They have outlined a roadmap at the Intel Connect event to deliver a two-year Cadence of Technologies, with the next one being Intel 14a.

Ensuring a resilient supply chain involves having a global manufacturing footprint, high security in offerings, and elements like advanced packaging, high-speed interconnects, and software optimization to enable system capability.

Intel has transitioned from 2D packaging solutions to systems of chips, with investments in 2 and half and 3D packaging technologies. They have significantly increased wafer level industry capacity and advanced capabilities to meet the growing demand for AI and high-performance computing.

Intel currently has over 100 2 and a2d designs in manufacturing, with solutions that can accommodate nearly 50 chips in a package. They possess key capabilities in power delivery, thermal management, advanced packaging technologies, and system technology co-optimization to support system Foundry design and packaging architecture.

Intel offers a range of advanced packaging technologies, including 2D FP fcbga, 2 and 1 half and 3D e to an FD, emib, FAS, and em 32d. These technologies support high-density interconnects, low resistance die-to-die connections, and system of chips integration.

Fora Direct 3D technology features Copp direct copper bonding, providing the highest density and lowest resistance die-to-die interconnects. It offers a power performance per bit of about 0.005 PJ per bit, emphasizing the focus on high-speed interconnects and system integration.

Intel's 18a technology includes power via ribbon fet, which delivers backside power and clocking, reducing iio drop by up to 30% and improving fmax by 6%. For inductive power supply droop, Intel offers a high-density MIM technology with 400 ftto per square Micron, providing 5x the amount of capacitance.

In 2019, Intel formed the Design Enablement Group to focus on design customers, recognizing the importance of design enablement in bringing designs to market quickly and leveraging technology effectively. This shift aimed to align Intel with industry methodologies and tools, tripling the number of Eda tools enabled on Intel's technologies.

Intel invested heavily in improving design ease of use, particularly in the 18a technology, to enhance competitiveness. The goal was to make designing in Intel's technology easier and more accessible for customers, addressing previous perceptions of Intel not being the easiest to design in.

Intel shifted towards a more open and collaborative approach, partnering deeply with equipment suppliers and Eda partners. Regular reviews and knowledge exchange sessions were established to leverage industry learnings and accelerate readiness for technology and design, fostering a culture of collaboration and openness.

Intel prioritized quality by building a QA organization, refining methodologies, and ensuring high-quality pdks and foundational IPS. Collaborating with Eda partners, Intel implemented feedback to align with industry standards, emphasizing a service-oriented business model with strong customer focus and support.

The speaker discusses their experience in customer support at Foundry, where they developed a web-based system to improve customer experience with design manuals. They innovated by creating a system that allows users to quickly locate errors in their designs and find solutions, enhancing ease of use and efficiency.

The speaker highlights the expansion of EDA (Electronic Design Automation) tools support, showcasing various tools for PDK, circuit simulation, custom layout, APR fill extraction, and physical verification. They emphasize the importance of enabling a wide range of tools to meet customer needs, leading to a significant effort over three years to enable key tools on Intel 16, Intel 3, and Intel 18a technologies.

The speaker mentions a strategic focus on enabling 3D and advanced packaging solutions, partnering with EDA suppliers to support 3D IC technology. They aim to provide a comprehensive suite of tools for both EMIB and FAS technologies, with a commitment to completing the enablement of all tools in the coming quarters.

The speaker discusses the collaboration with EDA suppliers to optimize design technology co-optimization (DTCO) early in the pathfinding stage. They emphasize working closely with partners like Synopsys and Cadence to maximize power, performance, and area efficiency on 14a technology. Additionally, they highlight the development of new EDA tooling for capabilities like power via, resulting in significant improvements in power, performance, and area.

The speaker emphasizes the importance of understanding how to partition the design in a 3D system to achieve optimal performance, power, and area. They discuss the need for continued work and support from EDA partners to refine tools for design partitioning, floor planning, power wiring, and thermal constraints.

While acknowledging the early stages of 3D design capabilities, the speaker highlights the ongoing need for improvement. They mention the necessity for physical design implementation tools to handle multiple variants of TSVs, manage thermomechanical stresses, and perform static timing analysis across multiple dies efficiently.

The speaker outlines the components of a comprehensive 3D system design kit, including design methodology flow, enabled PDks for 2D and 3D solutions, advanced packaging solutions, foundational IP, and a strong EDA ecosystem. They stress the importance of system technology co-optimization to achieve the best power, performance, and area in technology design.

In conclusion, the speaker asserts that System Foundry and the system of chips are not just future concepts but are relevant today. They express confidence in the capabilities of the 3D system design kit to deliver optimal results in power, performance, and area.